The invention relates to a field-effect-controlled transistor which is functional even with channel lengths of less than 50 nm.
Planar MOS and junction transistors come up against their functional limits at a channel length of about 50 nm. Various transistor structures have been proposed for the gate length range below 50 nm (see, for example, H. Wong et al., IEDM 97, page 427 et seq.). One proposal here is for a MOS transistor to be provided with two gate electrodes which are arranged on mutually opposite sides of the channel region and thus control a current flow along two surfaces of the channel region. Here there are both vertical structures, in which a source region, the channel region and a drain region are arranged in the vertical direction with regard to a main surface of a silicon wafer and form a stack projecting above the main surface, and planar structures, in which the source region, the channel region and the drain region are arranged parallel to the main surface of the silicon wafer.
H. Wong et al., IEDM 97, page 427 et seq., have proposed realizing a planar MOS transistor on an SOI substrate, in which one gate electrode is arranged above, and one gate electrode below, the channel region. In order to fabricate the transistor, it is proposed to apply to a silicon substrate a thick silicon oxide layer, a first silicon nitride layer, a first thin silicon oxide layer, a spacer layer made of amorphous silicon, a second thin silicon oxide layer and a second silicon nitride layer and to pattern them in such a way that the surface of the thick silicon oxide layer is uncovered in the regions for source and drain. Furthermore, in one of the source/drain regions, a window is opened in the thick silicon oxide layer down to the surface of the silicon substrate. The spacer layer made of amorphous silicon is removed in the region of the gate stack. Afterward, by means of selective epitaxy proceeding from the uncovered surface of the silicon substrate, monocrystalline silicon is grown in the region of the source/drain regions and of the channel region. Removal of the patterned first silicon nitride layer and second silicon nitride layer and deposition of doped polysilicon result in the formation of the two gate electrodes above and below the channel region which grew in the course of the selective epitaxy. This method is not compatible with standard steps of semiconductor process technology.
D. Hisamoto et al., IEDM 89, pages 833-36, have proposed a planar MOS transistor having a source region, a channel region and a drain region in a silicon ridge which is insulated by a field oxide region from a silicon substrate arranged underneath. A gate electrode overlaps the silicon ridge in the region of the channel region and thus controls a channel current along both sidewalls of the silicon ridge. The current direction runs parallel to the main surface of the silicon substrate. In order to fabricate this transistor, it is proposed to pattern the silicon ridge on the surface of a silicon substrate, the ridge being covered with a silicon nitride layer and the sidewalls of the ridge being provided with silicon nitride spacers. The surface of the silicon substrate is subsequently undercut under the silicon nitride spacers. The field oxide region is formed by local oxidation of the surface of the silicon substrate. In this case, the oxidation is continued until field oxide regions produced on both sides of the ridge meet through the bird beaks that form below the ridge. This fabrication process is also not compatible with standard steps of semiconductor process technology.
The object of the present invention is to provide a field-effect-controlled transistor which overcomes the above-noted deficiencies and disadvantages of the prior art devices of this general kind, and which is functional with gate lengths of less than 50 nm and which can be fabricated using standard steps of semiconductor process technology. It is a further object of the invention to specify a method of fabricating a transistor of this type.
With the above and other objects in view there is provided, in accordance with the invention, a field-effect-controlled transistor, comprising:
a semiconductor substrate having a main surface;
an active region with sidewalls, the active region having a source region, a drain region, and a channel region, each adjoining the main surface of the semiconductor substrate;
the main surface having a first trench and a second trench formed therein adjoining mutually opposite sidewalls of the active region;
a gate electrode formed with two conductive spacers on opposite sides of the active region and at the channel region and a patterned conductive layer connecting the conductive spacers;
an insulation structure filling the first trench and the second trench, with the conductive spacers lying between the active region and the insulation structure, and the conductive layer extending across the filled trenches; and
insulating fillings disposed in interspaces formed between two other mutually opposite sides of the active region and the insulation structure, the insulation fillings being disposed at the source region and the drain region and outside the patterned conductive layer.
The field-effect-controlled transistor is implemented in a semiconductor substrate. There is provided in the semiconductor substrate an active region having a source region, a channel region and a drain region, which each adjoin a main surface of the semiconductor substrate, so that a current flows between source region and drain region parallel to the main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate, which trench adjoins the channel region and in which trench a part of a gate electrode is arranged. In the transistor, a part of the gate electrode reaches into the depth of the semiconductor substrate, so that the gate electrode can be used to control a current which flows parallel to the main surface of the substrate in a sidewall of the channel region which intersects the main surface of the substrate. The effective channel width is thus independent of the width of the channel region at the main surface of the semiconductor substrate.
The transistor can be realized not only as a MOS transistor but also as a junction transistor. In the case of a MOS transistor, the surface of the channel region is provided with a gate dielectric at least in the region of the trench.
With regard to integration in standard silicon process technology, it is advantageous to use a semiconductor substrate which has monocrystalline silicon at least in the region of the main surface. In particular, a monocrystalline silicon wafer, the monocrystalline silicon layer of an SOI substrate, an SiGe substrate or an SiC substrate are suitable as semiconductor substrate.
Preferably, parts of the gate electrode are in each case arranged on mutually opposite sidewalls of the channel region, so that the transistor effectively has two mutually opposite gate electrode parts. These parts are respectively arranged in a first trench and a second trench. The provision of two gate electrode parts means that inversion channels are controlled on the mutually opposite sidewalls of the channel region. As a result, the drain voltage punch-through to the channel region is reduced, so that the limiting xe2x80x9cdrain induced barrier loweringxe2x80x9d known from the literature is practically ineffectual. Furthermore, the disturbing influence of the substrate voltage on the channel region is reduced by virtue of the provision of two gate electrode parts.
In accordance with an added feature of the invention, a gate dielectric is formed on the surface of the active region, at least in a region of the first and second trenches.
In accordance with an additional feature of the invention, an extent of the source region and of the drain region perpendicularly to the main surface is less than or equal to a depth of the trench. In other words, the extent of the source region and of the drain region perpendicularly to the main surface of the semiconductor substrate is less than or equal to the depth of the trench or the depth of the trenches. As a result, the area over which a conductive inversion channel forms is enlarged, so that the current yield is multiplied relative to planar arrangements. Moreover, the transistor transconductance, which is essential for the driving of the transistor, is thereby multiplied.
Preferably, the dimension of the gate electrode parallel to the main surface is restricted to the dimension of the channel region, thereby minimizing the drain-gate overlap capacitance. As a result, parasitic capacitances are minimized and an increased transistor transconductance is obtained, which is advantageous for fast switching behavior and a good radio-frequency behavior ranging into the GHz range.
In order to insulate the transistor within an integrated circuit, it is advantageous to provide an insulation structure which surrounds the active region and the trench or the trenches.
With the above and other objects in view there is provided, in accordance with the invention, a method of fabricating a field-effect-controlled transistor as outlined above. The novel method comprises the following steps:
producing a first trench and a second trench in a main surface of a semiconductor substrate, the trenches laterally defining an active region having a source region, a channel region, and a drain region, each adjoining the main surface of the semiconductor substrate;
depositing a first conductive layer, and forming from the first conductive layer, by anisotropic etching, conductive spacers on two mutually opposite sides of the active region;
producing an insulation structure surrounding the active region and the conductive spacers;
depositing a second conductive layer connected to the conductive spacers;
forming a gate electrode by patterning the second conductive layer and the conductive spacers; and
producing an interspace during the patterning of the conductive spacers at the source region and the drain region between the insulation structure and the active region, and filling the interspace with insulating material.
In accordance with a concomitant feature of the invention, he source region and the drain region are formed by implantation in a self-aligned manner with respect to the second conductive layer and the insulation structure.
In other words, in order to fabricate the transistor, a trench is produced in the main surface of the semiconductor substrate, which trench laterally defines the active region. A gate electrode which is partly arranged in the trench is then formed.
In order to fabricate the transistor as a MOS transistor, a gate dielectric is produced on the surface of the channel region.
In order to form the gate electrode in a self-aligning manner, a first conductive layer is deposited, from which layer, by means of anisotropic etching, conductive spacers are formed on the sidewalls of the active region. An insulation structure surrounding the active region and the conductive spacers is subsequently produced. The surface of the conductive spacers parallel to the main surface of the semiconductor substrate is uncovered. A second conductive layer is deposited, which is connected to the conductive spacers via the uncovered surface thereof. The gate electrode is formed by patterning the second conductive layer and the conductive spacers. In particular, doped polycrystalline or amorphous silicon, metal silicide and/or metal is suitable as material for the conductive layers. The patterning in order to complete the gate electrode is preferably effected by means of masked etching. The mask used in the process defines the gate length. By using a fine patterning step, for example electron beam lithography, an imprint method, or by employing a spacer technique, it is possible here to obtain gate lengths of less than 50 nm, in particular from 10 to 50 nm.
The source/drain regions are preferably fabricated in a self-aligned manner with respect to the gate electrode by means of implantation.
The trench preferably has a cross section corresponding to the cross section of the insulation structure and the gate electrode. In this case, the insulation structure is formed for example by deposition of an insulating layer, which completely fills the trench, and chemical mechanical polishing.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a field-effect-controlled transistor and method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.